US 12,299,411 B2
Processing with compact arithmetic processing element
Joseph Bates, Newton, MA (US)
Assigned to Singular Computing LLC, Newton, MA (US)
Filed by Singular Computing LLC, Newton, MA (US)
Filed on Dec. 8, 2023, as Appl. No. 18/533,372.
Application 18/533,372 is a continuation of application No. 18/073,972, filed on Dec. 2, 2022, granted, now 11,842,166.
Application 18/073,972 is a continuation of application No. 17/029,780, filed on Sep. 23, 2020, granted, now 11,768,659, issued on Sep. 26, 2023.
Application 17/029,780 is a continuation of application No. 16/882,694, filed on May 25, 2020, granted, now 11,169,775, issued on Nov. 9, 2021.
Application 16/882,694 is a continuation of application No. 16/882,686, filed on May 25, 2020, granted, now 10,754,616, issued on Aug. 25, 2020.
Application 16/882,686 is a continuation of application No. 16/675,693, filed on Nov. 6, 2019, granted, now 10,656,912, issued on May 19, 2020.
Application 16/675,693 is a continuation of application No. 16/571,871, filed on Sep. 16, 2019, granted, now 10,664,236, issued on May 26, 2020.
Application 16/571,871 is a continuation of application No. 16/175,131, filed on Oct. 30, 2018, granted, now 10,416,961, issued on Sep. 17, 2019.
Application 16/175,131 is a continuation of application No. 15/784,359, filed on Oct. 16, 2017, granted, now 10,120,648, issued on Nov. 6, 2018.
Application 15/784,359 is a continuation of application No. 14/976,852, filed on Dec. 21, 2015, granted, now 9,792,088, issued on Oct. 17, 2017.
Application 14/976,852 is a continuation of application No. 13/849,606, filed on Mar. 25, 2013, granted, now 9,218,156, issued on Dec. 22, 2015.
Application 13/849,606 is a continuation of application No. 13/399,884, filed on Feb. 17, 2012, granted, now 8,407,273, issued on Mar. 26, 2013.
Application 13/399,884 is a continuation of application No. 12/816,201, filed on Jun. 15, 2010, granted, now 8,150,902, issued on Apr. 3, 2012.
Claims priority of provisional application 61/218,691, filed on Jun. 19, 2009.
Prior Publication US 2024/0103806 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/483 (2006.01); G06F 7/38 (2006.01); G06F 7/523 (2006.01); H03K 19/17728 (2020.01)
CPC G06F 7/483 (2013.01) [G06F 7/38 (2013.01); G06F 7/4833 (2013.01); G06F 7/5235 (2013.01); H03K 19/17728 (2013.01)] 36 Claims
OG exemplary drawing
 
1. A device comprising:
a silicon chip comprising a plurality of processing units;
wherein the plurality of processing units comprise a first plurality of custom silicon arithmetic elements;
wherein at least one of the first plurality of custom silicon arithmetic elements is adapted to execute a first multiplication operation on
one or more first inputs that represent a first numerical value using a floating point representation that has a signed binary mantissa of no more than 11 bits and a signed binary exponent of at least 6 bits, and
on one or more second inputs that represent a second numerical value using a floating point representation;
wherein a total number of the first plurality of custom silicon arithmetic elements in the silicon chip that are adapted to execute first multiplication operations exceeds, by at least N=20 more than three times, a total number of second custom silicon arithmetic elements in the silicon chip adapted to perform on each cycle the operation of traditional high-precision multiplication on floating point numbers that are at least 32 bits wide; and
wherein the first plurality of custom silicon arithmetic elements are adapted to collectively perform, per cycle, at least tens of thousands of first multiplication operations.