US 12,299,375 B2
Semiconductor process technology assessment
Hung-Chih Ou, Kaohsiung (TW); Kuo-Fu Lee, Hsinchu County (TW); Wen-Hao Chen, Hsinchu (TW); Keh-Jeng Chang, Hsinchu (TW); and Hsiang-Ho Chang, Miaoli County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 6, 2024, as Appl. No. 18/434,345.
Application 18/434,345 is a continuation of application No. 18/176,701, filed on Mar. 1, 2023, granted, now 11,928,416.
Application 18/176,701 is a continuation of application No. 17/231,194, filed on Apr. 15, 2021, granted, now 11,604,915, issued on Mar. 14, 2023.
Prior Publication US 2024/0176944 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/398 (2020.01); G06F 119/18 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2119/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of process technology assessment, comprising:
defining a scope of the process technology assessment by assessing changes between an original process technology that includes original layout parameters and a first process technology that includes first layout parameters;
modeling a first object in an integrated circuit into a first resistance in the first process technology and a first capacitance in the first process technology;
modeling a second object in the integrated circuit into a second resistance in the first process technology and a second capacitance in the first process technology;
generating a first resistance scaling factor that is based on the first resistance and the original process technology and a first capacitance scaling factor that is based on the first capacitance and the original process technology;
generating a second resistance scaling factor that is based on the second resistance and the original process technology and a second capacitance scaling factor that is based on the second capacitance and the original process technology;
inputting the first resistance scaling factor, the first capacitance scaling factor, the second resistance scaling factor, and the second capacitance scaling factor into an electronic design automation (EDA) tool;
inputting an original technology file corresponding to the original process technology into the EDA tool; and
utilizing, by the EDA tool, the first resistance scaling factor, the first capacitance scaling factor, the second resistance scaling factor, the second capacitance scaling factor, and the original technology file for simulation of the integrated circuit.