| CPC G06F 3/065 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |

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1. An electronic device comprising:
an input handling circuit configured to receive a first request including an address from a first memory device, to align the address with an access unit of a second memory device to generate an aligned address, to request a determination for the aligned address, and to transmit a second request to the second memory device based on a determination result;
a control circuit configured to determine, based on the request, whether a duplicate address that is a duplicate with the aligned address is present to generate the determination result and to update a bitmask based on the determination result; and
a data transfer circuit configured to receive data corresponding to the second request from the second memory device and to transfer the data based on the bitmask,
wherein the bitmask comprises one or more bits, each corresponding to the first request and indicating a location corresponding to the first request within an access unit of the second memory device.
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