	US 12,299,301 B2
	Methods and systems for altering the path of data movement for large-sized memory transactions
Hithesh Hassan Lepaksha, Hyderabad (IN); Darshan Kumar Nandanwar, Bangalore (IN); and Sharath Kumar Nagilla, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on Apr. 26, 2023, as Appl. No. 18/307,686.
Prior Publication US 2024/0361931 A1, Oct. 31, 2024
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0888 (2016.01); G06F 12/0897 (2016.01)

CPC G06F 3/0635 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0685 (2013.01); G06F 12/0804 (2013.01); G06F 12/0811 (2013.01); G06F 12/0888 (2013.01); G06F 12/0897 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/502 (2013.01)]

20 Claims

1. A method for performing memory transactions in a way that reduces data movement in a memory hierarchy comprising:

determining with a processor whether or not a type of memory transaction being queued in one or more cores of the processor for execution by the processor is one of a plurality of preselected types for which data path alteration is an option;

determining with the processor whether or not a size of a memory block in a system memory associated with the memory transaction exceeds a first preselected size threshold, S_TH₁, value;

selecting with a last level cache (LLC) controller an altered path of data movement for performing the memory transaction if determinations are made that the memory transaction type is one of the preselected types and that the memory block size exceeds the S_TH₁value, and wherein the selected altered path reduces an amount of data movement relative to unaltered paths of data movement that are used for performing memory transactions that are not of the preselected types; and

causing the memory transaction to be performed using the altered path of data movement when the memory transaction is one of the plurality of preselected types.