| CPC G06F 3/0635 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0683 (2013.01)] | 20 Claims |
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1. An apparatus comprising:
at least one processing device comprising a processor coupled to a memory;
the at least one processing device being configured:
to maintain in a host device a plurality of queue depth measures for respective ones of a plurality of paths over which input-output operations are delivered from the host device to a storage system; and
to control path selection for delivery of additional input-output operations from the host device to the storage system based at least in part on the queue depth measures maintained for the plurality of paths;
wherein a given one of the queue depth measures provides an indication of a number of pending input-output operations for the corresponding path; and
wherein the at least one processing device comprises a plurality of processing cores of the host device and further wherein a first one of the plurality of processing cores is designated from among the plurality of processing cores to update the queue depth measures on behalf of all of the processing cores and is configured to update the queue depth measures for respective ones of the plurality of paths based at least in part on inter-core messages received by the first processing core from respective other ones of the plurality of processing cores, the inter-core messages received by the first processing core from the respective other ones of the plurality of processing cores indicating respective numbers of pending input-output operations for the respective other ones of the processing cores, the inter-core messages being stored in a lockless circular ring buffer of the first processing core;
the first processing core obtaining information from respective ones of the inter-core messages received from the respective other ones of the processing cores, and generating the updated queue depth measures utilizing the obtained information, the obtained information indicating, for a corresponding one of the respective other ones of the processing cores, one or more pending input-output operations of that processing core for at least one of the plurality of paths;
the updated queue depth measures generated by the first processing core being utilized by each of the first processing core and the other ones of the processing cores in selecting paths for delivery of corresponding ones of the additional input-output operations from the respective processing cores of the host device to the storage system.
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