US 12,299,280 B2
Namespace size adjustment in non-volatile memory devices
Alex Frolikov, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 7, 2024, as Appl. No. 18/598,100.
Application 18/598,100 is a continuation of application No. 17/870,642, filed on Jul. 21, 2022, granted, now 11,928,332.
Application 17/870,642 is a continuation of application No. 16/859,800, filed on Apr. 27, 2020, granted, now 11,435,900, issued on Sep. 6, 2022.
Application 16/859,800 is a continuation of application No. 15/790,969, filed on Oct. 23, 2017, granted, now 10,642,488, issued on May 5, 2020.
Prior Publication US 2024/0211130 A1, Jun. 27, 2024
Int. Cl. G06F 3/06 (2006.01); G06F 12/10 (2016.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0631 (2013.01); G06F 3/064 (2013.01); G06F 3/0652 (2013.01); G06F 3/0664 (2013.01); G06F 3/0683 (2013.01); G06F 12/10 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/65 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
non-volatile storage media having a logical address capacity divided into a plurality of first blocks according to a predetermined block size; and
a circuit configured to, responsive to a first command to create a namespace:
allocate a first subset of the first blocks for the namespace;
update an ordered list to include at least block identifications of blocks in the first subset; and
store, in association with the namespace, a first indication of an address of the block identifications in the ordered list, and a second indication of whether the blocks in the first subset are contiguous in the logical address capacity;
wherein the device is further configured to perform translations of logical addresses from the namespace to the logical address capacity based on the ordered list, the first indication, and the second indication.