US 12,298,926 B2
High-performance, high-capacity memory systems and modules
Frederick A. Ware, Los Altos Hills, CA (US); Ely Tsern, Los Altos, CA (US); John Eric Linstadt, Palo Alto, CA (US); Thomas J. Giovannini, San Jose, CA (US); Craig E. Hampel, Los Altos, CA (US); Scott C. Best, Palo Alto, CA (US); and John Yan, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Aug. 4, 2023, as Appl. No. 18/365,696.
Application 17/507,588 is a division of application No. 15/525,379, abandoned, previously published as PCT/US2015/060057, filed on Nov. 11, 2015.
Application 18/365,696 is a continuation of application No. 17/507,588, filed on Oct. 21, 2021, granted, now 11,755,508.
Claims priority of provisional application 62/203,279, filed on Aug. 10, 2015.
Claims priority of provisional application 62/085,802, filed on Dec. 1, 2014.
Prior Publication US 2024/0020249 A1, Jan. 18, 2024
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1678 (2013.01) [G06F 13/1673 (2013.01); G06F 13/1694 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory module comprising:
a first memory component;
a second memory component;
an address-buffer component including:
a primary address interface to receive a primary memory address;
a primary chip-select interface to receive primary chip-select information;
a first secondary chip-select interface connected to the first memory component;
a second secondary chip-select interface connected to the second memory component;
the address-buffer component including:
a mode register to store a mode signal indicative of one of a first operational mode and a second operational mode; and
a multiplexer coupled to the primary address interface and the primary chip-select interface to select one of the primary memory address and the primary chip-select information responsive to the mode signal;
wherein the address-buffer component, in the first operational mode, steers the primary chip-select information to one of the first and second secondary chip-select interfaces and disables the other of the first and second secondary chip-select interfaces responsive to the selected one of the primary memory address and the primary chip-select information.