| CPC G06F 13/1631 (2013.01) [G06F 12/0238 (2013.01); G06F 12/06 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/7209 (2013.01)] | 20 Claims |

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1. An apparatus configured to identify a set of M output memory addresses from a larger set of N input memory addresses, the apparatus comprising:
a comparator block configured to perform comparisons of memory addresses from a set of N input memory addresses to generate a classification dataset that identifies a subset of unique addresses from the set of input addresses;
a plurality of combination logic units, each configured to: receive a subset of data from the classification dataset and order the subset of data into two groups, wherein a first group identifies addresses belonging to the subset of unique addresses, and a second group identifies addresses not belonging to the subset of unique addresses; and
output generating logic configured to select between data belonging to different subsets of data to generate an output identifying at least one address in the subset of unique addresses.
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