US 12,298,922 B2
Peripheral interconnect controller
Pål Håland, Trondheim (NO); and Carsten Wulff, Trondheim (NO)
Assigned to Nordic Semiconductor ASA, Trondheim (NO)
Appl. No. 18/039,362
Filed by Nordic Semiconductor ASA, Trondheim (NO)
PCT Filed Dec. 1, 2021, PCT No. PCT/NO2021/050247
§ 371(c)(1), (2) Date May 30, 2023,
PCT Pub. No. WO2022/119448, PCT Pub. Date Jun. 9, 2022.
Claims priority of application No. 2018921 (GB), filed on Dec. 1, 2020.
Prior Publication US 2024/0004805 A1, Jan. 4, 2024
Int. Cl. G06F 13/12 (2006.01)
CPC G06F 13/122 (2013.01) 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a plurality of peripherals each peripheral comprising one or more event outputs or task inputs;
a peripheral interconnect, coupled to each of the peripheral event outputs and peripheral task inputs;
a controller for configuring the peripheral interconnect;
a memory; and
a bus system, communicatively coupled to the controller and to the memory,
wherein the peripheral interconnect comprises:
an input for receiving configuration data from the controller; and
circuitry, responsive to the received configuration data, for selectively connecting peripheral event outputs to peripheral task inputs, and
wherein the controller is configured to:
access, over the bus system, a script comprising a sequence of instructions, stored in the memory, the sequence comprising a first instruction and one or more subsequent instructions, wherein each instruction identifies a first peripheral event output, a peripheral task input, and a second peripheral event output;
implement each instruction of the sequence of instructions by sending respective configuration data to the peripheral interconnect for configuring the peripheral interconnect to connect the first peripheral event output identified by the instruction to the peripheral task input identified by the instruction; and
implement each subsequent instruction in the sequence of instructions in response to detecting an event signalled from the second peripheral event output identified by the preceding instruction in the sequence of instructions.