US 12,298,920 B2
Memory access during memory calibration
Ian Shaeffer, Los Gatos, CA (US); and Frederick A. Ware, Los Altos Hills, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Feb. 28, 2024, as Appl. No. 18/590,200.
Application 18/590,200 is a continuation of application No. 17/945,616, filed on Sep. 15, 2022, granted, now 11,947,468.
Application 17/945,616 is a continuation of application No. 17/022,746, filed on Sep. 16, 2020, granted, now 11,474,957, issued on Oct. 18, 2022.
Application 17/022,746 is a continuation of application No. 16/266,526, filed on Feb. 4, 2019, granted, now 10,810,139, issued on Oct. 20, 2020.
Application 16/266,526 is a continuation of application No. 15/485,115, filed on Apr. 11, 2017, granted, now 10,210,102, issued on Feb. 19, 2019.
Application 15/485,115 is a continuation of application No. 14/871,754, filed on Sep. 30, 2015, granted, now 9,652,409, issued on May 16, 2017.
Application 14/871,754 is a continuation of application No. 13/883,542, granted, now 9,176,903, issued on Nov. 3, 2015, previously published as PCT/US2011/059550, filed on Nov. 7, 2011.
Claims priority of provisional application 61/411,897, filed on Nov. 9, 2010.
Prior Publication US 2024/0330207 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/14 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01)
CPC G06F 12/1458 (2013.01) [G06F 3/0619 (2013.01); G06F 12/023 (2013.01); G06F 13/16 (2013.01); G06F 13/1657 (2013.01); G06F 13/1684 (2013.01); G06F 13/1694 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/1052 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller to control a first memory device including a plurality of first banks where each first bank has a plurality of first sub-banks that is each selectable by a sub-bank address corresponding to the first sub-bank, the memory controller comprising:
a first data interface circuit to couple to the first memory device via a first data bus and transmit a first calibration pattern to the first memory device; and
a command interface to transmit to the first memory device, a first refresh command including a sub-bank address of a first sub-bank of the plurality of first sub-banks for refresh,
wherein the memory controller performs a first calibration operation on the first data interface circuit responsive to the first data interface circuit receiving a response to the first calibration pattern from the first memory device, wherein the first calibration operation is performed while the first sub-bank corresponding to the sub-bank address is being refreshed.