US 12,298,916 B2
Page request interface support in handling host submission queues and completion automation associated with caching host memory address translation data
Prateek Sharma, San Jose, CA (US); Raja V. S. Halaharivi, Gilroy, CA (US); Sumangal Chakrabarty, Campbell, CA (US); and Venkat R. Gaddam, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 22, 2023, as Appl. No. 18/517,370.
Claims priority of provisional application 63/427,561, filed on Nov. 23, 2022.
Prior Publication US 2024/0168891 A1, May 23, 2024
Int. Cl. G06F 12/123 (2016.01); G06F 12/0882 (2016.01)
CPC G06F 12/123 (2013.01) [G06F 12/0882 (2013.01); G06F 2212/1021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory sub-system controller comprising:
host interface circuitry to interact with a host system and comprising:
a host queue interface circuit to interact with submission queues of the host system; and
an address translation circuit, coupled to the host queue interface circuit, the address translation circuit to handle address translation requests to the host system from the host queue interface circuit, the address translation circuit comprising a cache to store address translations associated with the address translation requests;
wherein the host queue interface circuit is to:
pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that has missed at the cache;
trigger a page request interface (PRI) handler to send a page miss request to a translation agent of the host system, the page miss request including a virtual address of the address translation request;
receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the translation agent; and
restart command arbitration on the submission queue that had been paused responsive to the restart message.