US 12,298,915 B1
Hierarchical store queue circuit
Nikhil Gupta, Santa Clara, CA (US); Gideon N. Levinsky, Cedar Park, TX (US); Kulin N. Kothari, Cupertino, CA (US); Mridul Agarwal, Saratoga, CA (US); and Pankaj Lnu, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 26, 2023, as Appl. No. 18/359,755.
Int. Cl. G06F 12/123 (2016.01); G06F 9/30 (2018.01)
CPC G06F 12/123 (2013.01) [G06F 9/30043 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
in response to determining that a primary queue has an available entry, placing, by a hierarchal store queue circuit, received store requests into the primary queue;
in response to determining that the primary queue has no available entries, placing, by the hierarchal store queue circuit, subsequently received store requests into a secondary queue;
committing, by the hierarchal store queue circuit, store requests from the primary queue to a cache memory circuit;
in response to determining that the primary queue has an available entry, identifying an oldest store request currently held in the secondary queue; and
relocating the oldest store request from the secondary queue to the primary queue.