US 12,298,912 B1
Enhanced write buffer flush scheme for memory devices with high density storage memory architecture
Rajesh Kumar Biswal, Puri (IN); Manmeet Singh Ahluwalia, Bangalore (IN); Surendra Paravada, Hyderabad (IN); Madhu Yashwanth Boenapalli, Hyderabad (IN); and Sai Praneeth Sreeram, Anantapur (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Nov. 14, 2023, as Appl. No. 18/509,066.
Int. Cl. G06F 12/0891 (2016.01); G06F 12/02 (2006.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0238 (2013.01); G06F 2212/7203 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory controller:
coupled to a write buffer and configured to access data stored at the write buffer, the write buffer having a single-level cell (SLC) memory architecture;
coupled to a memory module through a first channel and configured to access data stored at the memory module through the first channel, the memory module having a higher storage density memory architecture than the write buffer; and
coupled to a host device through a first interface and configured to communicate with the host device over the first interface,
the memory controller configured to perform operations comprising:
maintaining a list of data segments stored in the write buffer, the list including, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed, wherein the list is sorted based on the available contiguous memory space;
detecting a flush opportunity associated with the write buffer;
initiating, based on detection of the flush opportunity, a flush operation to write a first data segment from the write buffer to the memory module, the first data segment corresponding to the first entry of the list;
receiving, from the host device and prior to completion of the flush operation, a write command associated with the write buffer;
pausing performance of the flush operation upon receiving the write command, the flush operation having written a portion of the first data segment to the memory module; and
writing, based on the write command, a new data segment to the write buffer.