| CPC G06F 12/0811 (2013.01) [G06F 12/1009 (2013.01)] | 18 Claims |
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1. A computer system for initializing a memory, the computer system comprising:
a processor core comprising a central processing unit (CPU), a load store unit, and an internal cache; and
a last level cache in communication with the processor core, the last level cache comprising a cache pipeline, the last level cache configured to:
receive bulk store operations from the load store unit, each bulk store operation including a physical address in the memory to be initialized;
send multiple first write transactions to the cache pipeline for each bulk store operation;
send a corresponding multiple second write transactions from the cache pipeline to the memory for each bulk store operation to perform a bulk initialization of the memory for each bulk store operation; and
track status of the bulk store operations, wherein the cache pipeline in the last level cache is configured to maintain cache coherence in a hierarchy of caches in the computer system responsive to receiving each first write transaction and prior to sending the corresponding second write transaction to the memory.
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