US 12,298,903 B2
Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refresh
Kunal Desai, Bangalore (IN); Saurabh Jaiswal, Kaushambi (IN); Vikrant Kumar, Bangalore (IN); Swaraj Sha, Bangalore (IN); and Dharmesh Parikh, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 9, 2023, as Appl. No. 18/314,167.
Application 18/314,167 is a division of application No. 17/174,073, filed on Feb. 11, 2021, granted, now 11,749,332.
Prior Publication US 2023/0274774 A1, Aug. 31, 2023
Int. Cl. G06F 12/06 (2006.01); G11C 11/406 (2006.01)
CPC G06F 12/0607 (2013.01) [G11C 11/40618 (2013.01); G06F 12/06 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A method of portion interleaving for asymmetric size memory portions of a memory, comprising:
receiving an address of a memory access request in the memory;
mapping the address to a first interleave granule in a first asymmetric memory portion, wherein mapping the address to the first interleave granule in the first asymmetric memory portion comprises:
determining a consumed address space offset for consumed address space of the memory in a second asymmetric memory portion; and
modifying the address using the consumed address space offset;
assigning consecutive interleave units to the first interleave granule while the first interleave granule has unused space before assigning another interleave unit to another interleave granule, wherein at least a first interleave unit of the consecutive interleave units corresponds to the address; and
implementing the memory access request at the mapped address within the first asymmetric memory portion.