US 12,298,899 B2
Memory system and address verification method
Akira Matsuo, Kawasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on May 31, 2023, as Appl. No. 18/326,093.
Claims priority of application No. 2022-089719 (JP), filed on Jun. 1, 2022.
Prior Publication US 2023/0393974 A1, Dec. 7, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 12/0292 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/2022 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory; and
a controller capable of communicating with a host and configured to control the nonvolatile memory,
wherein the controller is configured to:
generate a first information based on an address translation table holding a correspondence relationship between a logical address and a physical address, the logical address indicating a logical location on the nonvolatile memory, the physical address indicating a physical location on the nonvolatile memory based on a request from the host, the first information being associated with the logical address,
transmit the first information to the host,
when the controller receives a read command including the logical address and the first information from the host, determine validity of the first information for the logical address,
regarding a logical address in which data is written and with which a physical address is associated, generate the first information including identification information indicating that data is written and the associated physical address,
regarding a logical address in which data is not written and with which no physical address is associated, generate the first information including identification information indicating that data is not written and a logical address with which no physical address is associated, and
when the identification information included in the first information in the read command indicates that data is not written, as the determination of the validity, compare the logical address included in the read command with the logical address included in the first information in the read command.