US 12,298,897 B2
Architectural support for persistent applications
Mazen Alwadi, Irbid (JO); Vamsee Reddy Kommareddy, Leander, TX (US); Clayton Hughes, Albuquerque, NM (US); Simon David Hammond, Albuquerque, NM (US); and Amro Awad, Morrisville, NC (US)
Assigned to National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US); and University of Central Florida Research Foundation, Inc., Orlando, FL (US)
Filed by National Technology & Engineering Solutions of Sandia, LLC, Albuquerque, NM (US); and University of Central Florida Research Foundation, Inc., Orlando, FL (US)
Filed on Feb. 4, 2022, as Appl. No. 17/665,390.
Prior Publication US 2023/0251963 A1, Aug. 10, 2023
Int. Cl. G06F 12/02 (2006.01); G06F 8/65 (2018.01)
CPC G06F 12/0238 (2013.01) [G06F 8/65 (2013.01); G06F 2212/304 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A method of architectural support of hybrid memory system persistent applications, the method comprising:
caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory, the dynamic random access memory comprising a mirror mapping table comprising a hardware managed table,
wherein a memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when a first update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, using the memory controller hub to both write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory providing coherent persistent durability of the update,
wherein the hardware managed table includes for each mirrored page a group ID, a TAG (non-volatile memory page address) and a dynamic random access memory address.