US 12,298,872 B2
Glitch suppression apparatus and method
Avneep Kumar Goyal, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on May 15, 2023, as Appl. No. 18/317,420.
Application 18/317,420 is a continuation of application No. 17/152,901, filed on Jan. 20, 2021, granted, now 11,687,428.
Prior Publication US 2023/0281092 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 1/06 (2006.01); G06F 11/22 (2006.01); G06F 11/263 (2006.01)
CPC G06F 11/263 (2013.01) [G06F 1/06 (2013.01); G06F 11/2236 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a main core processor configured to receive a plurality of signals, each signal received through a respective main buffer coupled to an input of the main core processor;
a shadow core processor configured to receive the plurality of signals, each signal received through a respective shadow buffer coupled to an input of the shadow core processor; and
a first glitch suppression buffer coupled to a common node of an input of a first main buffer and an input of a first shadow buffer, wherein the first glitch suppression buffer comprises a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, and a delay buffer, a first input of the first NAND gate coupled to a first input of the second NAND gate and an output of the delay buffer, a second input of the first NAND gate coupled to a first input of the third NAND gate and an output of the fourth NAND gate, a second input of the second NAND gate coupled to a second input of the third NAND gate and an input of the delay buffer, and an output of the first NAND gate, an output of the second NAND gate, and an output of the third NAND gate coupled to a respective input of the fourth NAND gate.