CPC G06F 11/167 (2013.01) [H10B 63/00 (2023.02); G06F 2201/805 (2013.01)] | 6 Claims |
1. A memory cell array unit, comprising:
a memory cell array including:
a plurality of n-bit allocation memory cells to which an n-bit allocation bit is allocated from a memory controller; and
a plurality of redundant memory cells; and
a microcontroller configured to:
determine a presence of a defective memory cell in the plurality of n-bit allocation memory cells;
write n-bit data into the plurality of n-bit allocation memory cells, based on the presence of the defective memory cell and a write control operation of the memory controller; and
write, based on the write control operation, first data of a bit corresponding to the defective memory cell into a redundant memory cell of the plurality of redundant memory cells,
wherein the n-bit data includes the first data.
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