	US 12,298,869 B2
	Memory cell array unit
Lui Sakai, Kanagawa (JP); and Yasuo Kanda, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/248,113
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Oct. 7, 2021, PCT No. PCT/JP2021/037181 § 371(c)(1), (2) Date Apr. 6, 2023, PCT Pub. No. WO2022/085471, PCT Pub. Date Apr. 28, 2022.
Claims priority of application No. 2020-175667 (JP), filed on Oct. 19, 2020.
Prior Publication US 2023/0385165 A1, Nov. 30, 2023
Int. Cl. G06F 11/16 (2006.01); H10B 63/00 (2023.01)

CPC G06F 11/167 (2013.01) [H10B 63/00 (2023.02); G06F 2201/805 (2013.01)]

6 Claims

1. A memory cell array unit, comprising:

a memory cell array including:

a plurality of n-bit allocation memory cells to which an n-bit allocation bit is allocated from a memory controller; and

a plurality of redundant memory cells; and

a microcontroller configured to:

determine a presence of a defective memory cell in the plurality of n-bit allocation memory cells;

write n-bit data into the plurality of n-bit allocation memory cells, based on the presence of the defective memory cell and a write control operation of the memory controller; and

write, based on the write control operation, first data of a bit corresponding to the defective memory cell into a redundant memory cell of the plurality of redundant memory cells,

wherein the n-bit data includes the first data.