US 12,298,849 B2
Dynamic control of error management and signaling
Michael Dieter Richter, Ottobrunn (DE); Thomas Hein, Munich (DE); Wolfgang Anton Spirkl, Germering (DE); Martin Brox, Munich (DE); and Peter Mayer, Neubiberg (DE)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Feb. 7, 2024, as Appl. No. 18/435,652.
Application 18/435,652 is a continuation of application No. 17/963,367, filed on Oct. 11, 2022, granted, now 11,914,467.
Application 17/963,367 is a continuation of application No. 17/486,751, filed on Sep. 27, 2021, granted, now 11,494,258, issued on Nov. 8, 2022.
Application 17/486,751 is a continuation of application No. 16/711,354, filed on Dec. 11, 2019, granted, now 11,138,064, issued on Oct. 5, 2021.
Claims priority of provisional application 62/779,024, filed on Dec. 13, 2018.
Prior Publication US 2024/0176695 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G01K 1/024 (2021.01)
CPC G06F 11/1004 (2013.01) [G01K 1/024 (2013.01); G06F 11/1068 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array;
error correction code logic associated with the memory array and configured, based at least in part on a command, to generate a first error correction code for data, detect one or more errors in the data, and correct the one or more errors in the data; and
an error counter associated with the error correction code logic and configured to be incremented based at least in part on the error correction code logic detecting the one or more errors in the data.