US 12,298,841 B1
Failure prediction of field-deployed mission critical integrated circuit chips using artificial intelligence
Shekaripuram V. Venkatesh, Los Altos, CA (US); and Tonatiuh Rangel Gordillo, San Jose, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Mar. 20, 2023, as Appl. No. 18/186,887.
Claims priority of provisional application 63/321,663, filed on Mar. 19, 2022.
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06N 3/091 (2023.01)
CPC G06F 11/0751 (2013.01) [G06N 3/091 (2023.01)] 21 Claims
OG exemplary drawing
 
1. A method for predicting failure of an integrated circuit (IC) chip, the method comprising:
identifying a logic block, comprised of one or more transistors and one or more interconnects, and a graph neural network (GNN) machine learning model to analyze the logic block;
training the GNN machine learning model based on one or more features comprised of the one or more transistors and the one or more interconnects and one or more labels comprised of path delays based on a subcritical path and a critical path in the logic block, the GNN training model trained for predicting a path delay at a next time interval in the logic block by:
triggering a timer to start and increment by a time, t, through a look back period;
identifying for each increment of time, t, a feature of the one or more features that influences a label of the one or more labels;
accumulating each identified feature and influenced label; and
transmitting back the accumulated identified features and influenced labels to the GNN machine learning model to predict the path delay at the next time interval;
determining whether the predicted path delay for the logic block will reach a failure threshold; and
generating automatically a notification in response to the failure threshold being reached.