US 12,298,838 B2
Grouping power supplies for a sleep mode
Ki-Jun Nam, Boise, ID (US); Yantao Ma, Boise, ID (US); Yasushi Matsubara, Isehara (JP); and Takamasa Suzuki, Hachioji (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 5, 2022, as Appl. No. 17/960,718.
Application 17/960,718 is a continuation of application No. 16/890,819, filed on Jun. 2, 2020, granted, now 11,487,346.
Prior Publication US 2023/0109187 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G11C 11/22 (2006.01)
CPC G06F 1/3296 (2013.01) [G06F 1/3275 (2013.01); G11C 11/221 (2013.01); G11C 11/2297 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a set of internal power supplies associated with a plurality of respective voltage levels, the set of internal power supplies comprising:
a first subset of internal power supplies associated with respective voltage levels different than a set of external power supply voltage levels; and
a second subset of internal power supplies associated with respective voltage levels different than the set of external power supply voltage levels; and
a set of on-die timers configured to generate a set of signals to adjust the respective voltage levels associated with the first subset of internal power supplies and the respective voltage levels associated with the second subset of internal power supplies in a first order upon an entry of a sleep mode, wherein the first order is programmed by the set of on-die timers.