US 12,298,826 B2
Semiconductor memory device and memory system
Akio Sugahara, Yokohama Kanagawa (JP); Yasuhiro Hirashima, Kawasaki Kanagawa (JP); and Naoya Tokiwa, Fujisawa Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 9, 2023, as Appl. No. 18/181,488.
Application 18/181,488 is a continuation of application No. PCT/JP2020/035698, filed on Sep. 23, 2020.
Prior Publication US 2023/0213993 A1, Jul. 6, 2023
Int. Cl. G06F 1/28 (2006.01); G11C 16/04 (2006.01)
CPC G06F 1/28 (2013.01) [G11C 16/0483 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first pin configured to receive a first signal and a second signal having a smaller amplitude than the first signal;
a first receiving circuit connected to the first pin and configured to output a third signal and a fourth signal having a smaller amplitude than the third signal, the first receiving circuit outputting the third signal based on a comparison between the first signal and a first voltage, and the first receiving circuit outputting the fourth signal based on a comparison between the second signal and a second voltage;
a first terminating circuit connected to the first pin and configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal;
a second pin configured to receive a fifth signal and a sixth signal having a smaller amplitude than the fifth signal;
a second receiving circuit connected to the second pin and configured to output a seventh signal and an eighth signal having a smaller amplitude than the seventh signal, the second receiving circuit outputting the seventh signal based on a comparison between the fifth signal and the first voltage, and the second receiving circuit outputting the eighth signal based on a comparison between the sixth signal and the second voltage;
a second terminating circuit connected to the second pin and configured to be disabled if the second pin receives the fifth signal and enabled if the second pin receives the sixth signal;
a third pin configured to receive a ninth signal and a tenth signal having a smaller amplitude than the ninth signal;
a third receiving circuit connected to the third pin and configured to output an eleventh signal and a twelfth signal having a smaller amplitude than the eleventh signal, the third receiving circuit outputting the eleventh signal based on a comparison between the ninth signal and the first voltage, and the third receiving circuit outputting the twelfth signal based on a comparison between the tenth signal and the second voltage; and
a third terminating circuit connected to the third pin and configured to be disabled if the third pin receives the ninth signal and enabled if the third pin receives the tenth signal.