US 12,298,632 B2
Liquid crystal display device comprising a pixel portion having a plurality of transistors
Ryo Hatsumi, Kanagawa (JP); Daisuke Kubota, Kanagawa (JP); and Hiroyuki Miyake, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Nov. 4, 2024, as Appl. No. 18/936,635.
Application 18/936,635 is a continuation of application No. 18/779,714, filed on Jul. 22, 2024.
Application 18/779,714 is a continuation of application No. 18/142,341, filed on May 2, 2023.
Application 18/142,341 is a continuation of application No. 17/949,661, filed on Sep. 21, 2022, granted, now 11,675,236, issued on Jun. 13, 2023.
Application 17/949,661 is a continuation of application No. 17/550,081, filed on Dec. 14, 2021, granted, now 11,460,737, issued on Oct. 4, 2022.
Application 17/550,081 is a continuation of application No. 17/026,702, filed on Sep. 21, 2020, granted, now 11,226,517, issued on Jan. 18, 2022.
Application 17/026,702 is a continuation of application No. 16/784,640, filed on Feb. 7, 2020, granted, now 10,782,565, issued on Sep. 22, 2020.
Application 16/784,640 is a continuation of application No. 15/995,287, filed on Jun. 1, 2018, granted, now 10,585,319, issued on Mar. 10, 2020.
Application 15/995,287 is a continuation of application No. 14/467,174, filed on Aug. 25, 2014, granted, now 9,989,796, issued on Jun. 5, 2018.
Claims priority of application No. 2013-177345 (JP), filed on Aug. 28, 2013; and application No. 2014-047301 (JP), filed on Mar. 11, 2014.
Prior Publication US 2025/0076712 A1, Mar. 6, 2025
Int. Cl. G02F 1/1343 (2006.01); G02F 1/1333 (2006.01); G02F 1/1337 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/134318 (2021.01) [G02F 1/133345 (2013.01); G02F 1/133707 (2013.01); G02F 1/134363 (2013.01); G02F 1/13624 (2013.01); G02F 1/134345 (2021.01); G02F 1/134372 (2021.01); G02F 2201/121 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A liquid crystal display device comprising:
a pixel portion including a plurality of pixels arranged in matrix, the plurality of pixels including a first pixel, a second pixel, and a third pixel arranged in a first direction;
a first conductive film having a region extending in parallel or substantially parallel to the first direction, and configured to be a gate electrode of a first transistor, a gate electrode of a second transistor, a gate electrode of a third transistor, and a first scan line;
a second conductive film having a region extending in a second direction crossing the first direction, and configured to be one of a source electrode and a drain electrode of the first transistor, and a first signal line;
a third conductive film configured to be the other of the source electrode and the drain electrode of the first transistor;
a fourth conductive film in contact with the third conductive film, and configured to be a pixel electrode of the first pixel;
a fifth conductive film having a region extending in parallel or substantially parallel to the second direction, and configured to be one of a source electrode and a drain electrode of the second transistor, and a second signal line;
a sixth conductive film configured to be the other of the source electrode and the drain electrode of the second transistor;
a seventh conductive film in contact with the sixth conductive film, and configured to be a pixel electrode of the second pixel;
an eighth conductive film having a region extending in parallel or substantially parallel to the second direction, and configured to be one of a source electrode and a drain electrode of the third transistor, and a third signal line;
a ninth conductive film configured to be the other of the source electrode and the drain electrode of the third transistor;
a tenth conductive film in contact with the ninth conductive film, and configured to be a pixel electrode of the third pixel; and
an eleventh conductive film overlapping the fourth conductive film, the seventh conductive film and the tenth conductive film, and configured to be a common electrode,
wherein the second pixel is interposed between the first pixel and the third pixel,
wherein in plan view, the eleventh conductive film has a first region, a second region, a third region spaced apart from each other by a first opening and a second opening, and a fourth region connected to the first region, the second region, and the third region,
wherein each of the first opening and the second opening has a region extending in parallel or substantially parallel to the first direction, and
wherein each of the regions of the first opening and the second opening has an area crossing the second conductive film, an area crossing the fifth conductive film, and an area crossing the eighth conductive film.