US 12,295,272 B2
Phase change memory
Laurent Favennec, Villard Bonnot (FR); and Fausto Piazza, Grenoble (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Jun. 22, 2022, as Appl. No. 17/847,016.
Claims priority of application No. 2107027 (FR), filed on Jun. 30, 2021.
Prior Publication US 2023/0006132 A1, Jan. 5, 2023
Int. Cl. H10N 70/20 (2023.01); H01L 23/522 (2006.01); H10B 63/10 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H01L 23/5226 (2013.01); H10B 63/10 (2023.02); H10N 70/011 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method for manufacturing a phase change memory, comprising:
forming an array of phase change memory cells, each cell being separated from neighboring cells in a same line of the array and from neighboring cells in a same column of the array, by a first distance; and
etching one memory cell out of N, where N is at least 2, in each line or each column.