| CPC H10N 50/80 (2023.02) [H10B 61/22 (2023.02); H10N 50/01 (2023.02)] | 20 Claims |

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1. A semiconductor device, comprising:
a substrate;
a first dielectric layer disposed on the substrate;
an etching stop layer disposed on the first dielectric layer;
a second dielectric layer disposed on the etching stop layer, wherein the first dielectric layer, the etching stop layer, and the second dielectric layer collectively define an opening; and
a conductive via disposed in the opening; and
a data storage structure disposed on the conductive via,
wherein the etching stop layer comprises a treated portion, and the treated portion comprises halide.
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