US 12,295,170 B2
Fabrication of gate-all-around integrated circuit structures having additive metal gates and gate dielectrics with a dipole layer
Dan S. Lavric, Beaverton, OR (US); Dax M. Crum, Beaverton, OR (US); Omair Saadat, Beaverton, OR (US); Oleg Golonzka, Beaverton, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2020, as Appl. No. 17/030,333.
Prior Publication US 2022/0093648 A1, Mar. 24, 2022
Int. Cl. H10D 86/00 (2025.01); H10D 86/01 (2025.01)
CPC H10D 86/201 (2025.01) [H10D 86/01 (2025.01)] 9 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type workfunction layer over a first gate dielectric comprising a high-k dielectric layer on a first dipole layer; and
a second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type workfunction layer over a second gate dielectric comprising the high-k dielectric layer on a second dipole layer, wherein the P-type workfunction layer has a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion, wherein the second portion of the P-type workfunction layer is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, and wherein the N-type workfunction layer has a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type workfunction layer, the second portion of the N-type workfunction layer over and on a top surface of the second portion of the P-type workfunction layer and covering the first portion of the P-type workfunction layer.