| CPC H10D 84/856 (2025.01) [H01L 23/5286 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/853 (2025.01)] | 14 Claims |
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1. A semiconductor device comprising
a first power supply line;
a second power supply line;
a ground line;
a first semiconductor area of a first conductive type;
a second semiconductor area of the first conductive type;
a third semiconductor area of the first conductive type located above the first semiconductor area and the second semiconductor area;
a fourth semiconductor area of the first conductive type located above the first semiconductor area and the second semiconductor area;
a first gate electrode located between the first semiconductor area and the second semiconductor area, and between the third semiconductor area and the fourth semiconductor area;
a fifth semiconductor area of a second conductive type;
a sixth semiconductor area of the second conductive type;
a seventh semiconductor area of a third conductive type, which is different from the second conductive type, located above the fifth semiconductor area and the sixth semiconductor area;
an eighth semiconductor area of the third conductive type located above the fifth semiconductor area and the sixth semiconductor area;
a second gate electrode located between the fifth semiconductor area and the sixth semiconductor area, and between the seventh semiconductor area and the eighth semiconductor area;
a switch circuit which includes the first semiconductor area, the second semiconductor area, the third semiconductor area, the fourth semiconductor area and the first gate electrode;
a switch control circuit which includes the fifth semiconductor area, the sixth semiconductor area, the seventh semiconductor area, the eighth semiconductor area and the second gate electrode; and
wherein
the first semiconductor area and the third semiconductor area are electrically connected to the first power supply line;
the second semiconductor area and the fourth semiconductor area are electrically connected to the second power supply line;
the fifth semiconductor area is electrically connected to one of the first power supply line and the ground line;
the seventh semiconductor area is electrically connected to another of the first power supply line and the ground line; and
the sixth semiconductor area and the eighth semiconductor area are electrically connected to the first gate electrode.
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