US 12,295,161 B2
Trench isolation having three portions with different materials, and LDMOS FET including same
Rong-Ting Liou, Malta, NY (US); Man Gu, Malta, NY (US); Jeffrey B. Johnson, Essex Junction, VT (US); Wang Zheng, Ballston Lake, NY (US); Jagar Singh, Clifton Park, NY (US); and Haiting Wang, Clifton Park, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Jan. 24, 2022, as Appl. No. 17/582,550.
Prior Publication US 2023/0238428 A1, Jul. 27, 2023
Int. Cl. H10D 62/10 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01)
CPC H10D 62/116 (2025.01) [H01L 21/76224 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a trench isolation (TI) in a substrate, the TI including:
a lower portion including a first dielectric material and having a first width;
a middle portion including the first dielectric material and an outer second dielectric material; and
an upper portion including a third dielectric material and having a second width greater than the first width,
wherein the first, second and third dielectric materials are different,
wherein the third dielectric material contacts the first dielectric layer at a first portion of a material interface and the second dielectric material at a second portion of the material interface, and the third dielectric material has an uppermost surface coplanar with an uppermost surface of the substrate.