US 12,295,151 B2
Semiconductor structure and manufacturing method thereof
Pan Yuan, Hefei (CN); Xingsong Su, Hefei (CN); Qiang Zhang, Hefei (CN); and Zhan Ying, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 19, 2022, as Appl. No. 17/648,350.
Application 17/648,350 is a continuation of application No. PCT/CN2021/109969, filed on Aug. 2, 2021.
Claims priority of application No. 202110258253.9 (CN), filed on Mar. 9, 2021.
Prior Publication US 2022/0293720 A1, Sep. 15, 2022
Int. Cl. H10D 1/68 (2025.01); H01G 4/10 (2006.01); H10D 1/00 (2025.01); H10B 12/00 (2023.01)
CPC H10D 1/696 (2025.01) [H01G 4/10 (2013.01); H10D 1/042 (2025.01); H10D 1/694 (2025.01); H10D 1/716 (2025.01); H10B 12/30 (2023.02); H10D 1/68 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a base;
forming a bottom electrode layer on the base, wherein a crystal structure of the bottom electrode layer comprises a tetragonal crystal system;
forming a first dielectric layer on a surface of the bottom electrode layer by using the bottom electrode layer as a seed layer, wherein a crystal structure of the first dielectric layer comprises a tetragonal crystal system;
forming a first current blocking layer on a surface of the first dielectric layer; and
forming a second dielectric layer on the first current blocking layer; and depositing a second current blocking layer on a surface of the second dielectric layer, wherein a temperature of the depositing is greater than or equal to a crystallization temperature for a crystal structure of the second dielectric layer to be transformed into a tetragonal crystal system.