US 12,295,148 B2
Semiconductor memory device
Katsuyoshi Komatsu, Yokkaichi Mie (JP); Hiroki Tokuhira, Kawasaki Kanagawa (JP); Hiroshi Takehira, Yokkaichi Mie (JP); Hiroyuki Ode, Yokkaichi Mie (JP); and Jieqiong Zhang, Yokkaichi Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2022, as Appl. No. 17/901,485.
Claims priority of application No. 2022-043670 (JP), filed on Mar. 18, 2022.
Prior Publication US 2023/0301118 A1, Sep. 21, 2023
Int. Cl. H10B 63/00 (2023.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/845 (2023.02) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H10B 63/20 (2023.02); H10N 70/066 (2023.02); H10N 70/231 (2023.02); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first wiring extending in a first direction;
a second wiring extending in a second direction intersecting the first direction and spaced from the first wiring in a third direction intersecting the first direction and the second direction;
a stacked body disposed between the first wiring and the second wiring and including a plurality of conductive layers and a plurality of insulating layers, wherein the plurality of conductive layers and the plurality of insulating layers are alternately stacked on top of one another in the third direction;
a columnar body including: (a) an electrode disposed between the first wiring and the second wiring and extending in the third direction through the stacked body, (b) a memory layer disposed between the electrode and the plurality of conductive layers, and (c) a selection layer disposed between the electrode and the first wiring; and
a diode disposed between the electrode and the second wiring;
wherein the columnar body includes a first film along the electrode, and the selection layer and the memory layer each are a portion of the first film.