| CPC H10B 61/22 (2023.02) [H01L 21/02565 (2013.01); H01L 29/24 (2013.01); H10N 50/01 (2023.02)] | 20 Claims |
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1. A method of forming a semiconductor device, the method comprising:
depositing an insulation layer over a semiconductor substrate;
forming a bottom electrode layer in the insulation layer;
depositing a first dielectric layer over the bottom electrode layer and the insulation layer;
forming a conductive gate layer in the first dielectric layer;
depositing a second dielectric layer over the conductive gate layer and the first dielectric layer;
etching through the second dielectric layer, the conductive gate layer, and the first dielectric layer to form a plurality of openings that expose top surfaces of the bottom electrode layer;
depositing an oxide semiconductor layer in the plurality of openings to form channel regions of access transistors;
forming an isolation structure extending through the second dielectric layer, the conductive gate layer, and the first dielectric layer, wherein the isolation structure is disposed between a first access transistor of the access transistors and a second access transistor of the access transistors, wherein bottom surfaces of channel regions of the first access transistor and the second access transistor are below a bottom surface of the isolation structure, and wherein the bottom surface of the isolation structure is in physical contact with the bottom electrode layer; and
coupling the access transistors to one or more magnetic tunnel junctions (MTJs).
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