| CPC H10B 41/27 (2023.02) [H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 16 Claims |

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1. A three-dimensional (3D) memory device, comprising:
a stack structure comprising conductive layers and dielectric layers that are interleaved stacked in a vertical direction;
a doped semiconductor layer; and
a channel structure extending through the stack structure and in contact with the doped semiconductor layer, the channel structure comprising a composite dielectric film and a semiconductor channel both extending along the vertical direction, wherein
the composite dielectric film comprises a gate dielectric portion and a memory portion in contact with each other and aligned along the vertical direction,
a part of the gate dielectric portion is located on a lateral side of one of the conductive layers that is closest to the doped semiconductor layer,
the memory portion of the composite dielectric film comprises a blocking layer, a storage layer, and a tunneling layer stacking along the lateral direction,
the gate dielectric portion of the composite dielectric film comprises a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer along the lateral direction,
the blocking layer and the first gate dielectric layer comprise a same dielectric material,
the tunneling layer and the third gate dielectric layer comprise a same dielectric material, and
the storage layer and the second gate dielectric layer comprise different dielectric materials.
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