US 12,295,135 B2
Memory device, and semiconductor structure and forming method thereof
Shih-Hung Lee, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Mar. 28, 2022, as Appl. No. 17/656,769.
Application 17/656,769 is a continuation of application No. PCT/CN2021/112022, filed on Aug. 11, 2021.
Claims priority of application No. 202110067276.1 (CN), filed on Jan. 19, 2021.
Prior Publication US 2022/0231028 A1, Jul. 21, 2022
Int. Cl. H10B 12/00 (2023.01); G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/85 (2023.01)
CPC H10B 12/053 (2023.02) [G11C 11/161 (2013.01); H10B 12/34 (2023.02); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/85 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a source region and a drain region spaced apart from each other, and a gate trench located between the source region and the drain region;
forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; a thickness of a side of the interface layer away from a bottom of the gate trench being greater than a thickness of a side of the interface layer close to the bottom of the gate trench; and
etching back the side of the interface layer away from the bottom of the gate trench by using a wet etching process, such that a top height of the interface layer is lower than a top height of the conductive layer;
wherein the forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; a thickness of a side of the interface layer away from a bottom of the gate trench being greater than a thickness of a side of the interface layer close to the bottom of the gate trench comprises:
forming, in sequence on the inner wall of the gate trench, a fittedly attached gate oxide layer and a fittedly attached first interface layer, and a first conductive material that fills the gate trench;
etching the first conductive material by using a dry etching process, to expose a part of the first interface layer located on a side wall of the gate trench;
forming a second interface layer on a surface of the first interface layer located on the side wall of the gate trench, wherein the first interface layer and the second interface layer constitute the interface layer; and
depositing a second conductive material on a surface of the first conductive material away from the gate oxide layer, and wrapping the second interface layer around a periphery of the second conductive material, wherein a side of the second interface layer close to the bottom of the gate trench may be in contact with a remaining surface of the first conductive material away from the gate oxide layer.