US 12,295,133 B2
SRAM with backside cross-couple
Ruilong Xie, Niskayuna, NY (US); Albert M Chu, Nashua, NH (US); Carl Radens, LaGrangeville, NY (US); and Kisik Choi, Watervliet, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Apr. 25, 2022, as Appl. No. 17/660,431.
Prior Publication US 2023/0345691 A1, Oct. 26, 2023
Int. Cl. H10B 10/00 (2023.01); H10D 30/67 (2025.01)
CPC H10B 10/125 (2023.02) [H10D 30/6729 (2025.01); H10B 10/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An SRAM device comprising:
a frontside and a backside;
a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor;
a second PU transistor stacked over a second PD transistor; and
a backside cross-couple at the backside underneath the first and second PD transistors, the backside cross-couple connecting a first source/drain (S/D) region of the second PD transistor with a gate of the first PD transistor.