US 12,295,099 B2
Wiring board
Yuta Yamazaki, Nagano (JP)
Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed by SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed on Jun. 16, 2023, as Appl. No. 18/336,390.
Claims priority of application No. 2022-107610 (JP), filed on Jul. 4, 2022.
Prior Publication US 2024/0008179 A1, Jan. 4, 2024
Int. Cl. H05K 1/02 (2006.01); H05K 1/11 (2006.01)
CPC H05K 1/115 (2013.01) [H05K 1/0298 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/09827 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A wiring board comprising:
a first interconnect layer;
a first insulating layer covering the first interconnect layer;
a second interconnect layer including a first interconnect pattern formed on an upper surface of the first insulating layer, and a first via interconnect penetrating the first insulating layer and electrically connecting the first interconnect pattern and the first interconnect layer;
a second insulating layer provided on the first insulating layer; and
a third interconnect layer provided on the second insulating layer, wherein
the second insulating layer includes a first insulating film provided on the upper surface of the first insulating layer, and a second insulating film provided on an upper surface of the first insulating film,
the first interconnect pattern has a recess in an upper surface thereof located at a position on the first via interconnect,
the first insulating film covers an upper surface and a side surface of the first interconnect pattern, and fills the recess,
the upper surface of the first insulating film is flatter than the upper surface of the first interconnect pattern,
the first insulating film is thinner than the second insulating film,
the third interconnect layer includes a second interconnect pattern formed on an upper surface of the second insulating film, and a second via interconnect penetrating the first insulating film and the second insulating film, and
the second via interconnect of the third interconnect layer electrically connects the second interconnect layer and the third interconnect layer.