| CPC H05K 1/0231 (2013.01) [H05K 2201/09345 (2013.01); H05K 2201/09618 (2013.01); H05K 2201/09636 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10651 (2013.01)] | 5 Claims |
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1. A signal processing board comprising:
a six-layer substrate in which six wiring layers are stacked;
a first semiconductor element and a second semiconductor element arranged on an outer surface of a first layer of the six wiring layers;
a plurality of signal transmission planes formed in the first layer, a third layer, a fourth layer, and a sixth layer of the six wiring layers and electrically connected to one or both of the first semiconductor element and the second semiconductor element;
a first ground plane formed in a second layer of the six wiring layers and electrically connected to the first semiconductor element and the second semiconductor element;
a first power supply plane formed in a fifth layer of the six wiring layers and electrically connected to the first semiconductor element;
a second power supply plane formed in the fifth layer of the six wiring layers and electrically connected to the second semiconductor element;
a second ground plane formed in the fifth layer of the six wiring layers and electrically connected to the first semiconductor element and the second semiconductor element;
a first bypass capacitor arranged on an outer surface of the first layer or the sixth layer and electrically connected to the first power supply plane and the second ground plane; and
a second bypass capacitor arranged on an outer surface of the first layer or the sixth layer and electrically connected to the second power supply plane and the second ground plane.
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