| CPC H04W 74/0833 (2013.01) [H04W 36/0079 (2018.08); H04W 76/10 (2018.02)] | 30 Claims |

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1. A user equipment (UE), comprising:
one or more memories that store processor-executable code; and
one or more processors coupled with the one or more memories and configured to, when executing the code, cause the UE to:
transmit, as part of a two-step random access procedure, a portion of a first random access message including a random access preamble;
perform an unsuccessful listen-before-talk (LBT) procedure within a gap between the portion of the first random access message including the random access preamble and a physical uplink shared channel (PUSCH) occasion associated with the first random access message; and
monitor, within a response window that is associated with the two-step random access procedure and that follows the PUSCH occasion associated with the first random access message, a physical downlink control channel (PDCCH) to receive a second random access message in response to the first random access message, wherein the second random access message indicates one of: a success of the two-step random access procedure or a fallback to a four-step random access procedure.
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