US 12,294,805 B2
Imaging device, operation method thereof, and electronic device
Seiichi Yoneda, Isehara (JP); and Hiroki Inoue, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Feb. 22, 2024, as Appl. No. 18/584,020.
Application 18/584,020 is a continuation of application No. 17/768,972, granted, now 11,917,318, previously published as PCT/IB2020/060041, filed on Oct. 27, 2020.
Claims priority of application No. 2019-202403 (JP), filed on Nov. 7, 2019.
Prior Publication US 2024/0196117 A1, Jun. 13, 2024
Int. Cl. H04N 25/78 (2023.01); H04N 25/709 (2023.01); H04N 25/77 (2023.01); H10K 39/32 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/709 (2023.01); H04N 25/77 (2023.01); H10K 39/32 (2023.02)] 18 Claims
OG exemplary drawing
 
1. An imaging device comprising:
a plurality of pixels, one of the plurality of pixels comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer; and
a fourth layer over the third layer,
wherein the first layer comprises a first circuit,
wherein the first circuit comprises:
a first transistor;
a second transistor; and
a third transistor,
wherein the second layer comprises a second circuit,
wherein the second circuit comprises:
a fourth transistor; and
a fifth transistor,
wherein the third layer comprises a photoelectric conversion device,
wherein the fourth layer comprises:
a light-blocking layer;
an optical conversion layer; and
a microlens array,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and
wherein one of a source and a drain of the fifth transistor is electrically connected to one electrode of the photoelectric conversion device.