US 12,294,804 B2
Adaptive correlated multiple sampling
Jiayu Guo, Milpitas, CA (US); Hiroaki Ebihara, San Jose, CA (US); Liang Zuo, Milpitas, CA (US); Lihang Fan, Sunnyvale, CA (US); and Satoshi Sakurai, Cupertino, CA (US)
Assigned to OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on May 23, 2023, as Appl. No. 18/322,431.
Prior Publication US 2024/0397226 A1, Nov. 28, 2024
Int. Cl. H04N 25/78 (2023.01); H04N 25/616 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/616 (2023.01)] 21 Claims
OG exemplary drawing
 
1. An arithmetic logic circuit (ALU), comprising:
a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs of the GC generator in response to a comparator output;
a signal latch stage coupled to latch outputs of the front end latch stage in response to a signal latch enable signal;
a GC to binary stage coupled to generate a binary representation of the GC outputs latched in the signal latch stage;
an adder stage including first inputs and second inputs, wherein the first inputs of the adder stage are coupled to receive outputs of the GC to binary stage, wherein outputs of the adder stage are generated in response to the first inputs and the second inputs of the adder stage;
a pre-latch stage coupled to latch outputs of the adder stage in response to a pre-latch enable signal; and
a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal, wherein the second inputs of the adder stage are coupled to receive outputs of the feedback latch stage,
wherein the feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal,
wherein the ALU is configured to perform CMS calculations in response to the CMS feedback enable signal, and
wherein the ALU is configured to perform non-CMS calculations in response to the non-CMS feedback enable signal.