US 12,294,803 B2
Image sensor for performing an analog binning operation
Dong Ju Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Apr. 7, 2023, as Appl. No. 18/296,998.
Claims priority of application No. 10-2022-0112953 (KR), filed on Sep. 6, 2022.
Prior Publication US 2024/0080589 A1, Mar. 7, 2024
Int. Cl. H04N 25/78 (2023.01); H01L 27/146 (2006.01); H04N 25/46 (2023.01)
CPC H04N 25/78 (2023.01) [H01L 27/14609 (2013.01); H04N 25/46 (2023.01)] 14 Claims
OG exemplary drawing
 
1. An image sensor comprising:
a first pixel group including first to fourth unit pixel circuits arranged in at least one row;
a second pixel group including fifth to eighth unit pixel circuits arranged in at least one other row;
a third pixel group including ninth to 12th unit pixel circuits arranged in at least one other row;
a fourth pixel group including 13th to 16th unit pixel circuits arranged in at least one other row;
a first readout line disposed in a first column and connected to the first unit pixel circuit and the ninth unit pixel circuit;
a second readout line disposed in a second column and connected to the fifth unit pixel circuit and the 13th unit pixel circuit;
a third readout line disposed in a third column and connected to the second unit pixel circuit and the 10th unit pixel circuit;
a fourth readout line disposed in a fourth column and connected to the sixth unit pixel circuit and the 14th unit pixel circuit;
a fifth readout line disposed in a fifth column and connected to the third unit pixel circuit and the 11th unit pixel circuit;
a sixth readout line disposed in a sixth column and connected to the seventh unit pixel circuit and the 15th unit pixel circuit;
a seventh readout line disposed in a seventh column and connected to the fourth unit pixel circuit and the 12th unit pixel circuit;
an eighth readout line disposed in an eighth column and connected to the eighth unit pixel circuit and the 16th unit pixel circuit;
first to fourth readout circuits; and
a path selector suitable for, during a single row time in a binning mode, connecting the first to 16th unit pixel circuits to the first to fourth readout circuits via the first to eighth readout lines and connecting at least two readout lines of the first to eighth readout lines to one readout circuit of the first to fourth readout circuits.