US 12,294,801 B2
CAPMID design in VRFD for HDR structure
Zhe Gao, San Jose, CA (US); Ling Fu, Union City, CA (US); Qing Qin, Sunnyvale, CA (US); Zhiyong Zhan, Fremont, CA (US); and Tiejun Dai, Santa Clara, CA (US)
Assigned to OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Apr. 19, 2023, as Appl. No. 18/303,479.
Prior Publication US 2024/0357253 A1, Oct. 24, 2024
Int. Cl. H04N 25/77 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/77 (2023.01) [H04N 25/78 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a photodiode configured to photogenerate image charge in response to incident light;
a floating diffusion coupled to receive the image charge from the photodiode;
a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion;
a reset transistor coupled between a variable voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal; and
a lateral overflow integration capacitor (LOFIC) coupled between the variable voltage source and the floating diffusion,
wherein the variable voltage source is configured to output a high-voltage level during a high conversion gain (HCG) reset signal readout and an HCG image signal readout,
wherein the variable voltage source is configured to output a mid-voltage level during a LOFIC image signal readout and a LOFIC reset signal readout, and
wherein the variable voltage source is configured to output a low-voltage level during a rolling readout period.