US 12,294,800 B2
Solid-state imaging element
Hiroki Suto, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/256,353
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Nov. 9, 2021, PCT No. PCT/JP2021/041183
§ 371(c)(1), (2) Date Jun. 7, 2023,
PCT Pub. No. WO2022/130832, PCT Pub. Date Jun. 23, 2022.
Claims priority of application No. 2020-209606 (JP), filed on Dec. 17, 2020.
Prior Publication US 2024/0022837 A1, Jan. 18, 2024
Int. Cl. H04N 25/77 (2023.01); H01L 27/146 (2006.01); H03M 1/56 (2006.01); H04N 25/618 (2023.01); H04N 25/709 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/77 (2023.01) [H04N 25/709 (2023.01)] 8 Claims
OG exemplary drawing
 
1. A solid-state imaging element, comprising:
a pixel array that includes a first pixel and a second pixel, wherein
the first pixel is configured to output a first pixel signal, and
the second pixel is configured to output a second pixel signal;
a reference signal generation unit configured to generate a common reference signal;
a first reference signal input circuit configured to supply a first reference signal;
a second reference signal input circuit configured to supply a second reference signal;
a first comparator configured to compare the first pixel signal with the first reference signal; and
a second comparator configured to compare the second pixel signal with the second reference signal, wherein
the first reference signal input circuit is coupled to the reference signal generation unit via a common input wiring,
the first reference signal input circuit is configured to receive the common reference signal from the reference signal generation unit,
the second reference signal input circuit is coupled to the reference signal generation unit via the common input wiring,
the second reference signal input circuit is configured to receive the common reference signal from the reference signal generation unit,
the first reference signal input circuit is coupled to the first comparator via a common output wiring,
the first reference signal input circuit is configured to supply the first reference signal to the first comparator,
the second reference signal input circuit is coupled to the second comparator via the common output wiring,
the second reference signal input circuit is configured to supply the second reference signal to the second comparator,
the first reference signal input circuit includes a first transistor, a first switch, and a first current source,
the second reference signal input circuit includes a second transistor, a second switch, and a second current source,
a gate of the first transistor is coupled to the common input wiring,
a source of the first transistor is coupled to the common output wiring,
the first switch is coupled between the source of the first transistor and the first current source,
a gate of the second transistor is coupled to the common input wiring,
a source of the second transistor is coupled to the common output wiring, and
the second switch is coupled between the source of the second transistor and the second current source.