| CPC H04N 25/75 (2023.01) [H04N 25/59 (2023.01); H10F 39/18 (2025.01); H10F 39/8037 (2025.01)] | 20 Claims |
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1. A pixel circuit, comprising:
a photodiode configured to photogenerate image charge in response to incident light;
a floating diffusion coupled to receive the image charge from the photodiode;
a transfer transistor coupled between the photodiode and the floating diffusion to transfer the image charge from the photodiode to the floating diffusion;
a reset transistor coupled between a bias voltage source and the floating diffusion, wherein a drain of the reset transistor is coupled to the bias voltage source, wherein the reset transistor is configured to be switched in response to a reset control signal;
a source follower transistor having a gate coupled to the floating diffusion; and
a row select transistor coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a power line and a bitline; and
a lateral overflow integration capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to the drain of the reset transistor, wherein the second metal electrode is coupled to a source of the reset transistor and selectively coupled to the floating diffusion,
wherein the reset control signal is configured to turn on the reset transistor to couple the second metal electrode to the first metal electrode to discharge the LOFIC during an idle period occurring before an integration period,
wherein the row select transistor is configured to be switched in response to a row select control signal, and
wherein the row select control signal is configured to turn off the row select transistor during the idle period.
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