US 12,294,639 B2
Continuously changing system clock in a packet processing module based on load determined by deterministic feedback signals
Kenneth Edward Neudorf, Ottawa (CA)
Assigned to Ciena Corporation, Hanover, MD (US)
Filed by Ciena Corporation, Hanover, MD (US)
Filed on Dec. 18, 2023, as Appl. No. 18/542,963.
Application 18/542,963 is a continuation in part of application No. 18/354,075, filed on Jul. 18, 2023.
Prior Publication US 2025/0030533 A1, Jan. 23, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/033 (2006.01); H03L 7/08 (2006.01)
CPC H04L 7/033 (2013.01) [H03L 7/08 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A packet processing module comprising circuitry configured to:
receive feedback signals from each of N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1,
determine a clock speed for the packet processing module based on the received feedback signals, and
program a phase lock loop (PLL) based on the determined clock speed where the PLL provides a module clock at the determined clock speed to a packet processing circuit which is configured to receive and process packets from the N FIFOs,
wherein the feedback signals are each packet available signal which is asserted for each of the N FIFOs based on detection of a complete packet therein for processing by the packet processing circuit, and
wherein the determined clock speed is set based on a number of packet available signals asserted at a given time multiplied by a minimum clock frequency which is set equal to a maximum clock frequency divided by N.