US 12,294,519 B2
Packet processing device and packet processing method
Kuo Cheng Lu, Hsinchu (TW); Chun-Ming Liu, Hsinchu (TW); and Sheng Wen Lo, Hsinchu (TW)
Assigned to Realtek Semiconductor Corporation, Hsinchu (TW)
Filed by Realtek Semiconductor Corporation, Hsinchu (TW)
Filed on Mar. 13, 2023, as Appl. No. 18/182,386.
Claims priority of application No. 111131172 (TW), filed on Aug. 18, 2022.
Prior Publication US 2024/0064102 A1, Feb. 22, 2024
Int. Cl. H04L 47/12 (2022.01); H04L 47/24 (2022.01)
CPC H04L 47/12 (2013.01) [H04L 47/24 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A packet processing device, comprising:
a first ingress port;
a second ingress port;
a first egress port;
a second egress port, wherein a first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol, wherein the first packet flow and the third packet flow are transmitted from the first ingress port to the first egress port, and the second packet flow and the fourth packet flow are transmitted from the second ingress port to the second egress port; and
a bandwidth modulator, wherein when the packet processing device is in a congested state, the bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port,
wherein when the bandwidth modulator performs the first suppression process, the bandwidth modulator gradually decreases a bandwidth of the first packet flow at the first ingress port, wherein until the bandwidth of the first packet flow is equal to a lower bandwidth limit, the bandwidth modulator performs the second suppression process.