US 12,294,386 B2
Optimizations of memory-utilization and PCM processing schedules for an LDPC decoder
Vladimir Petrovic, Belgrade (RS); Dragomir El Mezeni, Belgrade (RS); and Milos Markovic, Belgrade (RS)
Assigned to TANNERA TECHNOLOGIES DOO, Belgrade (RS)
Filed by TANNERA TECHNOLOGIES DOO, Belgrade (RS)
Filed on Sep. 7, 2023, as Appl. No. 18/243,598.
Claims priority of application No. 23193404 (EP), filed on Aug. 25, 2023.
Prior Publication US 2025/0070797 A1, Feb. 27, 2025
Int. Cl. H03M 13/11 (2006.01); H03M 13/37 (2006.01)
CPC H03M 13/1148 (2013.01) [H03M 13/1105 (2013.01); H03M 13/1111 (2013.01); H03M 13/114 (2013.01); H03M 13/116 (2013.01); H03M 13/1162 (2013.01); H03M 13/1165 (2013.01); H03M 13/118 (2013.01); H03M 13/3707 (2013.01); H03M 13/3746 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus implementing a decoder with a layered decoder structure and the decoder configured to decode a sequence of codewords encoded with a low-density parity-check (LDPC) code using an iterative hybrid decoding algorithm, wherein the iterative hybrid decoding algorithm is based on passing messages between variable nodes and check nodes to decode a current codeword of the sequence of codewords in layers, the layers corresponding to portions of a parity check matrix (PCM) describing the LDPC code, wherein the iterative hybrid decoding algorithm includes a plurality of updates of log-likelihood ratios (LLRs) of a current codeword in decoding the current codeword, the apparatus comprising:
an LLR update unit implemented by processing elements and configured to calculate, in processing a current layer of said layers of the PCM, updated LLRs of the current codeword for those variable nodes for which the current layer of the PCM includes non-zero entries; and
an LLR memory, which is divided into a first memory block and a second memory block,
wherein the first memory block is to store the most recent updated LLRs of the current codeword, and
the second memory block stores LLRs of the next codework and, as patch LLRs, the most recent updated LLRs associated with a subset of the variable nodes for which a PCM processing schedule yields that variable-to-check messages from said associated variable nodes calculated in processing the current layer are not based on the most recent LLRs; and
wherein each of the first and second memory blocks comprises a first memory portion having a number of bits equal to the number of bits required to store the values of the LLRs of the current or next codeword, respectively, and a second portion having a number of bits that is smaller than that of the first portion to store said patch LLRs for the variable nodes prior to their update.