US 12,294,385 B1
Bit-flipping decoder and decoding method based on super node
Fan Zhang, San Jose, CA (US); Meysam Asadi, San Jose, CA (US); and Qiuju Diao, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 19, 2023, as Appl. No. 18/490,051.
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/37 (2006.01)
CPC H03M 13/1108 (2013.01) [H03M 13/3746 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a bit-flipping decoder, comprising:
receiving at a receiver of the bit-flipping decoder a codeword;
grouping two or more component nodes corresponding to two or more bits in the codeword to generate a super node; and
performing a decoding iteration on the super node containing the two or more component nodes grouped together,
wherein the decoding iteration includes:
calculating a flipping energy for the super node based on a flipping energy for each of the component nodes and internal checks between the component nodes;
flipping at least one of the two or more bits in the super node containing the two or more component nodes grouped together upon a determination that the flipping energy for the super node exceeds a bit-flipping threshold;
updating, subsequent to the flipping, a first syndrome as a product of the codeword and a parity check matrix; and
declaring a success of the decoding iteration upon a determination that the first syndrome is zero.