US 12,294,383 B1
High speed charge mode digital-to-analog converter
Eshel Gordon, Aloney Aba (IL); Boris Sharav, Yoqneam (IL); Roi Levi, Bruchin (IL); and Ayal Eshkoli, Kiryat Tivon (IL)
Assigned to MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on Jan. 18, 2021, as Appl. No. 17/151,348.
Int. Cl. H03M 1/66 (2006.01); H02H 9/04 (2006.01); H03M 1/36 (2006.01); H03M 1/68 (2006.01); H03M 3/00 (2006.01)
CPC H03M 1/68 (2013.01) [H02H 9/046 (2013.01); H03M 1/36 (2013.01); H03M 3/378 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system, comprising:
an input that receives a digital input signal;
circuitry comprising a first digital-to-charge converter and a second digital-to-charge converter, wherein the first digital-to-charge converter is charged based on the digital input signal and holds a first charge representing a first bit value of the digital input signal during a first pre-evaluation period, wherein the second digital-to-charge converter is charged based on the digital input signal and holds a second charge representing a second bit value of the digital input signal during a second pre-evaluation period;
a first set of switches that control charging and evaluation of the first digital-to-charge converter;
a second set of switches that control charging and evaluation of the second digital-to-charge converter, wherein the second set of switches comprises multiple switches not included in the first set of switches; and
an output that enables evaluation of the first charge and second charge held in the circuitry during an evaluation period that follows the first pre-evaluation period and the second pre-evaluation period, wherein the output provides an output signal in a charge domain that is based on the evaluation of the first charge and the second charge held in the circuitry, wherein:
the first digital-to-charge converter comprises a first plurality of capacitors that are charged according to the first bit value of the digital input signal at the first pre-evaluation period, wherein the first plurality of capacitors are subject to a first charge evaluation during a first evaluation period and output a first charge value representing the first bit value; and
the second digital-to-charge converter comprises a second plurality of capacitors that are charged according to the second bit value of the digital input signal at the second pre-evaluation period that is different from the first pre-evaluation period, wherein the second plurality of capacitors are subject toe a second charge evaluation during a second evaluation period and output a second charge value representing the second bit value.