| CPC H03L 7/0816 (2013.01) [H03K 5/135 (2013.01)] | 20 Claims |
|
1. A clock generating circuit comprising:
a first division circuit configured to generate a first group of internal clock signals by dividing a clock signal;
an internal circuit configured to generate a delayed clock signal by delaying the clock signal based on an enable signal;
a second division circuit configured to generate a second group of internal clock signals by dividing the delayed clock signal; and
an enable control circuit configured to generate the enable signal based on one of the first group of internal clock signals.
|